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hys64d[32/64]0x0edl?5?d hys64d[32/64]0x0edl?6?d 200-pin small-outline dual-in-line memory modules so-dimm ddr sdram internet data sheet rev. 1.00 january 2009
internet data sheet hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules qag_techdoc_a4, 4.22, 2008-07-22 2 05282008-iarq-5whu we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hys64d[32/64]0x0edl?5?d, hys64d[32/64]0x0edl?6?d revision history: 2009-01, rev. 1.00 page subjects (major chang es since last revision) all metadata change and document adapted to internet edition. previous revision: rev. 0.60, 2008-05 all added product type hys64d32000edl-[5/6]-d previous revision: rev. 0.50, 2007-09 all new document.
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 3 05282008-iarq-5whu 1overview this chapter contains features and the description. 1.1 features ? non-parity 200-pin small-outline dual-in-line memory modules ? one rank 32m 64, two ranks 64m 64 module organization and 32m 64 chip organization ? industry standard double-data-rate synchronous drams (ddr sdram) ? single +2.5 v ( 0.2 v) power supply and +2.6 v ( 0.1 v) for ddr400 ? built with 512-mbit ddr sdrams organised as 16 in packages p?tsopii?66 ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? industry standard form factor: 67.60 mm 31.75 mm 3.80 mm ? industry standard reference layout raw cards ?a? ? ddr400 speed grade supported ? gold plated contacts table 1 performance for ?5 and ?6 1.2 description the hys64d[32/64]0x0edl?5?d and hys64d[32/64]0x0edl?6?d are industry standard 200-pin small-outline dual-in-line memory modules (so-dimms) organized as 32m 64 and 64m 64. the memory array is designed with double-data-rate synchronous drams (ddr sdram). a variety of decoupling capacitors are mounted on the pcb. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. part number speed code ?5 ?6 unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 4 05282008-iarq-5whu table 2 odering information for lead-free (rohs compliant products) note: all product types end with a place code designating the silicon-die revision. reference information available on request. example: hys64d64020edl?5?d, indicating rev.b die ar e used for sdram components.the compliance code is printed on the module labels and describes the speed sort (f or example ?pc3200?), the latencies (for example ?30330? means cas latency of 3.0 clocks, row-column-delay (rcd) latency of 3 clocks and row precharge latency of 3 clocks), jedec spd code definition version 1, and the raw card used for this module. table 3 address format product type compliance code description sdram technology note 1) 1) rohs: restriction of the use of certain hazardous substances in electr ical and electronic equipment as defined in the directi ve 2002/95/ec issued by the european parliament and of the council of 27 januar y 2003. these substances include mercury, lead, cadmium, hexav alent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. pc3200 (cl=3.0) hys64d32000edl-5-d pc3200s?3033?1?c1 o ne rank 256mb so-dimm 512 mbit ( 16) hys64d64020edl-5-d pc3200s?3033?1?a1 two ranks 512mb so-dimm 512 mbit ( 16) pc2700 (cl=2.5) HYS64D32000EDL-6-D pc2700s?2533-1?c1 o ne rank 256mb so-dimm 512 mbit ( 16) hys64d64020edl-6-d pc2700s?2533-1?a1 two ranks 512mb so-dimm 512 mbit ( 16) density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 512mb 64m 64 2 32m 16 8 13/2/10 8k 64 ms 7.8 s 256mb 32m 64 1 32m 16 4 13/2/10 8k 64 ms 7.8 s
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 5 05282008-iarq-5whu 2 pin configuration 2.1 pin configuration the pin configuration of the unbuffered small outline ddr sdram dimm is listed by function in table 4 (200 pins). the abbreviations used in columns pin and buffer type are explained in table 5 and table 6 respectively. the pin numbering is depicted in figure 1 . table 4 pin configuration of so-dimm pin# name pin type buffer type function clock signals 35 ck0 i sstl clock signal 160 ck1 i sstl clock signal 89 ck2 i sstl clock signal note: ecc type module nc nc ? note: non-ecc type module 37 ck0 i sstl complement clock 158 ck1 i sstl complement clock 91 ck2 i sstl complement clock note: ecc type module nc nc ? note: non-ecc type module 96 cke0 i sstl clock enable rank 0 95 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 121 s0 i sstl chip select rank 0 122 s1 i sstl chip select rank 1 note: 2-ranks module nc nc ? note: 1-rank module 118 ras i sstl row address strobe 120 cas i sstl column address strobe 119 we i sstl write enable
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 6 05282008-iarq-5whu address signals 117 ba0 i sstl bank address bus 1:0 116 ba1 i sstl 112 a0 i sstl address bus 11:0 111 a1 i sstl 110 a2 i sstl 109 a3 i sstl 108 a4 i sstl 107 a5 i sstl 106 a6 i sstl 105 a7 i sstl 102 a8 i sstl 101 a9 i sstl 115 a10 i sstl ap i sstl 100 a11 i sstl 99 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 123 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 5 dq0 i/o sstl data bus 63:0 7 dq1 i/o sstl 13 dq2 i/o sstl 17 dq3 i/o sstl 6 dq4 i/o sstl 8 dq5 i/o sstl 14 dq6 i/o sstl 18 dq7 i/o sstl 19 dq8 i/o sstl 23 dq9 i/o sstl 29 dq10 i/o sstl 31 dq11 i/o sstl 20 dq12 i/o sstl 24 dq13 i/o sstl pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 7 05282008-iarq-5whu 30 dq14 i/o sstl data bus 63:0 32 dq15 i/o sstl 41 dq16 i/o sstl 43 dq17 i/o sstl 49 dq18 i/o sstl 53 dq19 i/o sstl 42 dq20 i/o sstl 44 dq21 i/o sstl 50 dq22 i/o sstl 54 dq23 i/o sstl 55 dq24 i/o sstl 59 dq25 i/o sstl 65 dq26 i/o sstl 67 dq27 i/o sstl 56 dq28 i/o sstl 60 dq29 i/o sstl 66 dq30 i/o sstl 68 dq31 i/o sstl 127 dq32 i/o sstl 129 dq33 i/o sstl 135 dq34 i/o sstl 139 dq35 i/o sstl 128 dq36 i/o sstl 130 dq37 i/o sstl 136 dq38 i/o sstl 140 dq39 i/o sstl 141 dq40 i/o sstl 145 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 142 dq44 i/o sstl 146 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 163 dq48 i/o sstl 165 dq49 i/o sstl 171 dq50 i/o sstl 175 dq51 i/o sstl 164 dq52 i/o sstl 166 dq53 i/o sstl pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 8 05282008-iarq-5whu 172 dq54 i/o sstl data bus 63:0 176 dq55 i/o sstl 177 dq56 i/o sstl 181 dq57 i/o sstl 187 dq58 i/o sstl 189 dq59 i/o sstl 178 dq60 i/o sstl 182 dq61 i/o sstl 188 dq62 i/o sstl 190 dq63 i/o sstl 71 cb0 i/o sstl check bit 0 note: ecc type module nc nc ? note: non-ecc module 73 cb1 i/o sstl check bit 1 note: ecc type module nc nc ? note: non-ecc module 79 cb2 i/o sstl check bit 2 note: ecc type module nc nc ? note: non-ecc module 83 cb3 i/o sstl check bit 3 note: ecc type module nc nc ? note: non-ecc module 72 cb4 i/o sstl check bit 4 note: ecc type module nc nc ? note: non-ecc module 74 cb5 i/o sstl check bit 5 note: ecc type module nc nc ? note: non-ecc module 80 cb6 i/o sstl check bit 6 note: ecc type module nc nc ? note: non-ecc module 84 cb7 i/o sstl check bit 7 note: ecc type module nc nc ? note: non-ecc module pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 9 05282008-iarq-5whu 11 dqs0 i/o sstl data strobes 7:0 note: see block diagram for corresponding dq signals 25 dqs1 i/o sstl 47 dqs2 i/o sstl 61 dqs3 i/o sstl 133 dqs4 i/o sstl 147 dqs5 i/o sstl 169 dqs6 i/o sstl 183 dqs7 i/o sstl 77 dqs8 i/o sstl data strobe 8 note: ecc type module nc nc ? note: non-ecc module 12 dm0 i sstl data mask 7:0 26 dm1 i sstl 48 dm2 i sstl 62 dm3 i sstl 134 dm4 i sstl 148 dm5 i sstl 170 dm6 i sstl 184 dm7 i sstl 78 dm8 i sstl data mask 8 note: ecc type module nc nc ? note: non-ecc module eeprom 195 scl i cmos serial bus clock 193 sda i/o od serial bus data 194 sa0 i cmos slave address select bus 2:0 196 sa1 i cmos 198 sa2 i cmos pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 10 05282008-iarq-5whu power supplies 1,2 v ref ai ? i/o reference voltage 197 v ddspd pwr ? eeprom power supply 9,10,21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 v dd pwr ? power supply pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 11 05282008-iarq-5whu 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 v ss gnd ? ground plane other pins 199 v ddid ood v dd identification note: pin in trista te, indicating v dd and v ddq nets connected on pcb 85, 86, 97, 98, 124, 200 nc nc ? not connected note: pins not connected on infineon so dimms pin# name pin type buffer type function
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 12 05282008-iarq-5whu table 5 abbreviations for pin type table 6 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or.
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 13 05282008-iarq-5whu figure 1 pin configuration diagram 200-pin so-dimm 0 3 3 ' 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 0 ' 4 9 ' ' ' 4 ' 0 ' 4 ' 4 ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 0 ' 4 ' 4 ' 4 & % 1 & & % 1 & & % 1 & & . ( $ $ $ % $ & $6 1 & ' 4 ' 4 ' 4 ' 0 ' 4 & . ' 4 ' 4 ' 4 ' 0 ' 4 6 $ 1 & 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 ' 4 9 ' ' ' 0 ' 4 & % 1 & ' 0 1 & 9 ' ' 1 & 9 6 6 9 ' ' 1 & $ $ $ 9 ' ' 5 $6 6 1 & ' 4 ' 0 ' 4 ' 4 ' 4 & . ' 4 ' 0 ' 4 ' 4 9 6 6 ' 4 6 $ 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 4 6 ' 4 9 ' ' & . ' 4 ' 4 6 ' 4 ' 4 ' 4 & . 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 6 ' 4 ' 4 ' 4 & % 1 & & % 1 & & % 1 & & . 1 & & . ( 1 & $ 1 & $ $ $ $3 : ( $ 1 & ' 4 ' 4 ' 4 ' 4 6 ' 4 ' 4 ' 4 ' 4 ' 4 6 ' 4 6 & / 9 ' ' , ' 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 4 6 ' 4 9 ' ' & % 1 & ' 4 6 1 & 9 ' ' 1 & & . 1 & 9 ' ' 1 & $ $ $ 9 ' ' % $ 6 ' 4 ' 4 6 ' 4 ' 4 ' 4 9 ' ' ' 4 ' 4 6 ' 4 ' 4 9 6 6 ' 4 6 ' $ 9 ' ' 6 3 ' 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 6 6 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 ' '
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 14 05282008-iarq-5whu 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 operating conditions this chapter contains the operating conditions tables. table 7 absolute maximum ratings attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be rest ricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause ir reversible damage to the integrated circuit. table 8 electrical characteristics and dc operating conditions parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1? w? short circuit output current i out ?50? ma? parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck > 166 mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5)
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 15 05282008-iarq-5whu input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 6) input low (logic0) voltage v il(dc) ? 0.3 v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ? 0.3 v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 6)7) vi-matching pull-up current to pull-down current v i ratio 0.71 1.4 ? 8) input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test = 0 v 9) output leakage current i oz ?5 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ?16.2 ? ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref.dc . v ref is also expected to tr ack noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) inputs are not recognized as valid until v ref stabilizes. 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . 8) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. 9) values are shown per pin. parameter symbol values unit note/test condition 1) min. typ. max.
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 16 05282008-iarq-5whu 3.2 current specification and conditions this chapter describes the specifications and conditions. table 9 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see co mponent data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changi ng twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2 ; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changin g on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2 ; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changin g on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 17 05282008-iarq-5whu table 10 i dd specification for hys64d64020edl?[5/6]?d product type hys64d64020edl-5-d hys64d64020edl-6-d unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c 512mb 512mb 64 64 2 ranks 2 ranks ?5 ?6 symbol typ. max. typ. max. i dd0 228 294 196 258 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd2p [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 260 330 224 290 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 837837ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 176 240 160 216 ma 5) i dd2q 120 176 112 160 ma 5) i dd3p 64 112 64 112 ma 5) i dd3n 232 296 208 272 ma 5) i dd4r 296 370 256 326 ma 3)4) i dd4w 284 358 248 314 ma 3) i dd5 496 602 444 522 ma 5) i dd6 12 32 12 32 ma 5) i dd7 712 870 600 686 ma 3)4)
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 18 05282008-iarq-5whu table 11 i dd specification for hys64d32000edl?[5/6]?d product type hys64d32000edl-5-d HYS64D32000EDL-6-D unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c 256mb 256mb 64 64 1 rank 1 rank ?5 ?6 symbol typ. max. typ. max. i dd0 224 276 192 240 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd2p [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 256 312 220 272 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 418418ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 88 120 80 108 ma 5) i dd2q 60 88 56 80 ma 5) i dd3p 32 56 32 56 ma 5) i dd3n 116 148 104 136 ma 5) i dd4r 292 352 252 308 ma 3)4) i dd4w 280 340 244 296 ma 3) i dd5 492 584 440 504 ma 5) i dd6 616616ma 5) i dd7 708 852 596 668 ma 3)4)
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 19 05282008-iarq-5whu 3.3 ac characteristics this chapter describes the ac characteristics. table 12 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 12 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsopii 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz +0.7 ?0.7 +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)8)
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 20 05282008-iarq-5whu address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)9) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ?7.8?7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 70 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 21 05282008-iarq-5whu 8) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 9) fast slew rate 1.0 v/ns, slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progres s on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progr ess, dqs could be high, low, or transiti oning from high to low at this time, depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 22 05282008-iarq-5whu 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 13 ?hys64d[32/64]3x0edl-[5/6]-d? on page 22 table 13 hys64d[32/64]3x0edl-[5/6]-d product type hys64d32000edl?5?d hys64d32000edl?6?d hys64d64020edl?5?d hys64d64020edl?6?d organization 256mb 256mb 512mb 512mb 64 64 64 64 1 rank ( 16) 1 rank ( 16) 2 ranks ( 16) 2 ranks ( 16) label code pc3200s? 30331 pc2700s? 25331 pc3200s? 30331 pc2700s? 25331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 40 40 40 40 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 60 50 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 11 error correction support 00 00 00 00 12 refresh rate 82 82 82 82 13 primary sdram width 10 10 10 10
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 23 05282008-iarq-5whu 14 error checking sdram width 00 00 00 00 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 1c 0c 1c 0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 75 60 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 75 00 75 00 26 t ac sdram @ cl max -1 [ns] 70 00 70 00 27 t rpmin [ns] 3c 48 3c 48 28 t rrdmin [ns] 28 30 28 30 29 t rcdmin [ns] 3c 48 3c 48 30 t rasmin [ns] 28 2a 28 2a 31 module density per rank 40 40 40 40 32 t as, t cs [ns] 60 75 60 75 33 t ah, t ch [ns] 60 75 60 75 34 t ds [ns] 40 45 40 45 35 t dh [ns] 40 45 40 45 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 37 3c 37 3c 42 t rfcmin [ns] 41 48 41 48 product type hys64d32000edl?5?d hys64d32000edl?6?d hys64d64020edl?5?d hys64d64020edl?6?d organization 256mb 256mb 512mb 512mb 64 64 64 64 1 rank ( 16) 1 rank ( 16) 2 ranks ( 16) 2 ranks ( 16) label code pc3200s? 30331 pc2700s? 25331 pc3200s? 30331 pc2700s? 25331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 24 05282008-iarq-5whu 43 t ckmax [ns] 28 30 28 30 44 t dqsqmax [ns] 28 2d 28 2d 45 t qhsmax [ns] 50 55 50 55 46 not used 00 00 00 00 47 dimm pcb height 01 01 01 01 48 - 61 not used 00 00 00 00 62 spd revision 10 10 10 10 63 checksum of byte 0-62 76 1a 77 1b 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 36 36 36 74 part number, char 2 34 34 34 34 75 part number, char 3 44 44 44 44 76 part number, char 4 33 33 36 36 77 part number, char 5 32 32 34 34 78 part number, char 6 30 30 30 30 79 part number, char 7 30 30 32 32 80 part number, char 8 30 30 30 30 product type hys64d32000edl?5?d hys64d32000edl?6?d hys64d64020edl?5?d hys64d64020edl?6?d organization 256mb 256mb 512mb 512mb 64 64 64 64 1 rank ( 16) 1 rank ( 16) 2 ranks ( 16) 2 ranks ( 16) label code pc3200s? 30331 pc2700s? 25331 pc3200s? 30331 pc2700s? 25331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 25 05282008-iarq-5whu 81 part number, char 9 45 45 45 45 82 part number, char 10 44 44 44 44 83 part number, char 11 4c 4c 4c 4c 84 part number, char 12 35 36 35 36 85 part number, char 13 44 44 44 44 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys64d32000edl?5?d hys64d32000edl?6?d hys64d64020edl?5?d hys64d64020edl?6?d organization 256mb 256mb 512mb 512mb 64 64 64 64 1 rank ( 16) 1 rank ( 16) 2 ranks ( 16) 2 ranks ( 16) label code pc3200s? 30331 pc2700s? 25331 pc3200s? 30331 pc2700s? 25331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 26 05282008-iarq-5whu 5 package outlines this chapter contains the package outlines of the products. figure 2 package outline so-dimm ra w card a (l-dim-200-6) notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/-0.15 0 , 1 ? ? ? ? ? ? ? ? ? ? 0 $ ; ? ? ? * / ' ' h w d l o r i f r q w d f w v ? ? % x u q l v k h g q r e x u u d o o r z h g
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 27 05282008-iarq-5whu figure 3 package outline so-dimm raw card c (l-dim-200-11) notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 ? ? ? ? ? ? ? ? 0 , 1 0 $; ? ? * /' ' h w d l o r i f r q w d f w v ? ? % x u q l v k h g q r e x u u d o o r z h g ? ?
hys64d[32/64]0x0edl?[5/6]?d small-outline ddr sdram modules internet data sheet rev. 1.00, 2009-01 28 05282008-iarq-5whu 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table of contents
edition 2009-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2009. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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